Senior Analog IC Design Engineer

Responsible for analog/mixed-signal IPs development for space applications ranging from schematics development through spice simulation, layout design guidance to post layout netlist extraction and simulation implementing radiation hardened by design techniques.

Designed Rad Hardened by Design LVDS and NVM IPs for space applications in 180nm technology. IPs ready for integration.

Designed several high- and core-voltage IPs for medical applications like brain stimulation.

Led analog/mixed-signal IPs development for various ASICs and SoCs from system architecture and technical specifications through schematics development, spice pre- and post-layout simulation to layout design guidance. Guided lab evaluation and issue investigation. Responsible for project technical lead and small design team management.

Key projects:

• Rad Hardened by Design direct digital synthesizer (DDS) for aerospace radio in 0.18um CMOS - designed 12-bit 300MSPS current steering DAC and led ADPLL and current reference with BGAP design
• USB 2.0 transceiver IP (PHY) in 0.18um LP CMOS - led development of all analog blocks
• Rad Hardened by Design SerDes PHY IPs (1.25Gbps and 3.125Gbps) in 0.18um and 90nm - performed system architecture design, supervised block development, designed phase interpolator and CDR samplers
• Low power ASIC in 0.18um CMOS with comparators, LDOs, 8-bit SAR ADC, references, oscillator and control circuit
• Heavy Ions Detector for aerospace with modified SRAM cells in 0.18um CMOS
• HV ASIC with LVDS interface in 0.25um BCD CMOS including LVDS receiver, HV power switches, protection circuits, BGAP, LDO
• Designed RHBD standard cell and IO libraries for aerospace projects
• Designed 60-80MHz and 2-10MHz RC-oscillators in 0.18um and 65nm CMOS

Responsible for circuit design, pre/post-layout simulations, layout design guidance, complex IC evaluation, and small digital circuits design.

Designed analog circuits for USB2.0 PHY, DVI PHY including AD-PLLs up to 1500MHz, USB1.1 cable repeater (UIC4102CP). Designed and characterized basic digital library in 0.18um CMOS and ECL digital library in 0.13um SiGe BiCMOS.