Yaroslav Gubin
Senior Analog IC Design Engineer
Experience
Senior Analog IC Design Engineer
IMEC
Responsible for analog/mixed-signal IPs development for space applications ranging from schematics development through spice simulation, layout design guidance to post layout netlist extraction and simulation implementing radiation hardened by design techniques.
Designed Rad Hardened by Design LVDS and NVM IPs for space applications in 180nm technology. IPs ready for integration.
Designed several high- and core-voltage IPs for medical applications like brain stimulation.
Senior Custom IC Design Engineer
Responsible for analog/mixed-signal IPs development for various ASICs including schematics development, spice pre- and post-layout simulations, layout design guidance. Responsible for technical guidance of other design engineers. Worked remotely with multinational teams.
Worked with Bitfury company on Bitcoin core custom design in near threshold power supply region with lowest power consumption. Developed several analog blocks for mining chip and support controller chip using 10nm and 5nm FinFET and 22nm FDSOI technologies.
Designed 12bit 30MS/s SAR ADC in 65nm CMOS, ready for test chip integration. Later ported to 130nm CMOS with 1MS/s sampling rate.
Analog/Mixed-Signal IC Team Lead
Digital Solutions
Led analog/mixed-signal IPs development for various ASICs and SoCs from system architecture and technical specifications through schematics development, spice pre- and post-layout simulation to layout design guidance. Guided lab evaluation and issue investigation. Responsible for project technical lead and small design team management.
Key projects:
- Rad Hardened by Design direct digital synthesizer (DDS) for aerospace radio in 0.18um CMOS - designed 12-bit 300MSPS current steering DAC and led ADPLL and current reference with BGAP design
- USB 2.0 transceiver IP (PHY) in 0.18um LP CMOS - led development of all analog blocks
- Rad Hardened by Design SerDes PHY IPs (1.25Gbps and 3.125Gbps) in 0.18um and 90nm - performed system architecture design, supervised block development, designed phase interpolator and CDR samplers
- Low power ASIC in 0.18um CMOS with comparators, LDOs, 8-bit SAR ADC, references, oscillator and control circuit
- Heavy Ions Detector for aerospace with modified SRAM cells in 0.18um CMOS
- HV ASIC with LVDS interface in 0.25um BCD CMOS including LVDS receiver, HV power switches, protection circuits, BGAP, LDO
- Designed RHBD standard cell and IO libraries for aerospace projects
- Designed 60-80MHz and 2-10MHz RC-oscillators in 0.18um and 65nm CMOS
Foundry Relations Manager
SensorIS
Managed IC Layout Design Group (4 engineers), handled interaction with Silicon Fabs on technical/technological issues and IP providers, prepared tapeout project data for MPW and engineering lots.
Successfully taped out 7 MPWs, 2 MLMs and 2 mass-produced ICs. Led layout designs of 6 ICs. Performed critical DRC and LVS verifications.
Senior IC Design Engineer
Unique ICs
Responsible for circuit design, pre/post-layout simulations, layout design guidance, complex IC evaluation, and small digital circuits design.
Designed analog circuits for USB2.0 PHY, DVI PHY including AD-PLLs up to 1500MHz, USB1.1 cable repeater (UIC4102CP). Designed and characterized basic digital library in 0.18um CMOS and ECL digital library in 0.13um SiGe BiCMOS.
IC Designer Intern
Unique ICs
Designed analog blocks (output drivers, receivers) for FireWire (IEEE1394) transceiver. Developed 1.5GHz integrated LNA for GLONASS application in GaAs technology including integrated inductors design.
Investigated frequency characteristics and q-factor dependence of integrated inductors using electromagnetic solver. Designed inductor for 1.5GHz LC VCO.
Industries Experience
See where this freelancer has spent most of their professional time. Longer bars indicate deeper hands-on experience, while shorter ones reflect targeted or project-based work.
Experienced in Manufacturing (21 years), Aerospace and Defense (10.5 years), Healthcare (5 years), Space Exploration (5 years), and Information Technology (4.5 years).
Business Areas Experience
The graph below provides a cumulative view of the freelancer's experience across multiple business areas, calculated from completed and active engagements. It highlights the areas where the freelancer has most frequently contributed to planning, execution, and delivery of business outcomes.
Experienced in Product Development (24.5 years), Research and Development (15 years), and Project Management (8 years).
Languages
Education
Moscow Institute of Physics and Technology (MIPT)
M. Sc. · Physical and Quantum Electronics (DPQE), Applied Physics and Mathematics · Russian Federation
Moscow Institute of Physics and Technology (MIPT)
B. Sc. · Physical and Quantum Electronics (DPQE), Applied Physics and Mathematics · Russian Federation
Profile
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