Henrik Møller Pedersen
ASIC Consultant
Experience
ASIC Consultant
Imec
- Setup vManager flow within IMEC with Jenkins Plugin
- vPlan, constraint-random verification, coverage, CRF regressions for IMEC Gen4 UWB modem
- Setup Stratus high level synthesis flow within IMEC
- Setup GitHub CI/CL flow for UWB
- IEEE 802.15.4a HRP UWB modem improvements: re-architecture and completely rewritten in SystemC, implemented with high level synthesis; quantization and resource-sharing refactor delivering 1/4 of the Gen4 size (area) while improving PER
- Soft-decision Viterbi (6-bit) with traceback depth 12; survivor memory and fixed-point widths tuned for robustness and latency using Matlab to Stratus flow
- Symbol timing and acquisition refined with Kalman filter and demodulator re-architecture
- Verification lead of the Seneca project in the last 2 months before tape-out
Lead Engineer
TII
- Design and verification/validation of true random number generator using a generalised ring oscillator and a Linear Hybrid Cellular Automata
- HLS design and verification of AES accelerator
- AES-GCM design and verification with minimalistic area and masked leakage; lab validation of side-channel leakage (ChipWhisperer)
- Xilinx SoC implementation with MicroBlaze platform and secure IP peripherals
- Constraint-random verification and SoC design of GF 22 nm ASIC for side-channel analysis
- Created Cadence Genus synthesis and Conformal flow; UPF 2.1 power-aware RTL simulations and GLS
- Principal reviewer of RTL and UVM verification framework of cryptographic hardware library
Senior Principal ASIC Specialist Consultant
imec – Holst Centre
- UWB ASIC: design and verification of sample-rate converters, de-spreaders, and Viterbi decoders; top-level verification and schedule adherence
- DARE6 radiation IP: clock-tree re-architecture; internal SRAM timing engines; reliability/performance analysis on imec IC-link DARE65 nm platform
ASIC Verification Consultant
Xilinx
- 5G NR PRACH UVM verification: test plan, sequences, constraint-random verification, coverage, CRF regressions
- Prepared written summaries of simulations and coverage analysis; achieved 100% functional and assertion coverage
Verification Lead Consultant
Ericsson
- Shark/Radon/Krypton 5G control subsystems: introduced CRV techniques; significant improvements in functional and code coverage
- Maintained functional coverage groups and UVM scoreboards; streamlined vManager vPlan regressions (Hansoft Scrum)
Expert ASIC Consultant
Huawei Technologies
- Top-level verification of 5G Direct Mode TX; UVM register-layer testbench (cycle and bit-accurate versus C++ reference); Jenkins CI
- Re-architected digital up-sampling chain and clock-tree resulting in ~50% power reduction; HLS synthesis of DPD; formal verification of IP blocks
Senior Principal ASIC Specialist Consultant
Frontier & EnSilica
- ARM Cortex-M3 mixed-signal SoC (battery charger): target IC spec, architecture design spec, IP selection; area and power tracking; DFT strategy
- NFC-powered smart card SoC (Cadence BBE16EP DSP): requirements, memory optimization, clock-gating and DVFS options; Jenkins CI; FPGA prototyping
- Sensium Healthcare WBAN 802.15.6 SoC: RTL for PMU, clock, AES-CCM, security engine, low-power heart-rate accelerator; SRAM arbitration; APB/ADC/RF interfaces
Principal Engineer
Micron Technology
- PCIe-connected AHCI/NVMe SSD virtualization; NVMe error management and high-availability architecture
- Verification of AHCI virtualization layers on FPGA; advanced NVMe SSD controller design
Senior ASIC Specialist
Nokia/Renesas
- Wireless Modem SoC front-end tech lead (GSM, LTE, 3G, DigRF); Viterbi decoders (enhanced SISO and list); low-power optimizations
- Power estimation and reduction (PowerTheater, PowerArtist); UPF power-aware simulations (VCS); Jenkins test automation; Certitude testbench and suite qualification
- Synopsys flow (DC, PrimeTime, PX) and Magma (Conformal, Blast); clock-tree optimization and power-gating; multi-site coordination
Industries Experience
See where this freelancer has spent most of their professional time. Longer bars indicate deeper hands-on experience, while shorter ones reflect targeted or project-based work.
Experienced in Manufacturing (12.5 years), Telecommunication (9 years), Information Technology (4 years), and Healthcare (1.5 years).
Business Areas Experience
The graph below provides a cumulative view of the freelancer's experience across multiple business areas, calculated from completed and active engagements. It highlights the areas where the freelancer has most frequently contributed to planning, execution, and delivery of business outcomes.
Experienced in Product Development (18 years), Quality Assurance (16.5 years), and Research and Development (7 years).
Summary
Strong technical expertise in lead, architecture, design and verification tasks of ASIC and FPGA design products in multicultural teams and international companies. I have in-depth knowledge of GSM/3G/LTE/5G and Ultra Wide Band standards and implementation as well as Ultrasonic/Radar designs. Outstanding skills in problem analysis and capability development. Well-versed in supervising cross-functional teams and completing first-time-right ASIC tape-outs.
Extensive experience in SoC and VLSI design and IP block implementation including high level synthesis.
Instrumental in managing ASIC and verification requirements resulting in high-quality verification closure with vManager or VC Execution Manager in a UVM framework. Excellent skills in establishing regression testing flows and verification plan development.
Verification experience with SystemVerilog / UVM workflow / formal verification / UPF power aware verification / gate level simulation / Certitude Functional Qualification System. Verification methods applied for advanced mixed signal SoC projects. Design and verification process control, method development, verification visibility and development of project KPIs.
I am proactive, I have attention to detail and timely execution. I am looking forward to working with technology driven companies.
Skills
- Asic & Fpga Design Solutions
- Signal Processing Algorithms
- Design For Test (Dft)
- System-on-chip (Soc) Designs
- Matlab, Simulink; Field Ii (Ultrasound Simulation)
- Verilog, Vhdl, Systemverilog; C, C++, Lisp; Perl, Python, Tcl, Shell
- System Architecture Verification; Requirement Management
- Power Analysis & Optimisation; Low Power Design Techniques; Upf Power-aware Verification
- Jenkins / Github Continuous Integration; Git/cvs/pcvs/svn
- Stratix; Genus; Conformal; Jaspergold; Vmanager; Xcelium/vcs/questa Sim
- Interfaces: Pcie, Digrf, Mipi, I2c, Spi; Amba Axi/axis/apb/ahb, Cpri …
- High Level Synthesis (Hls); Uvm & Formal Verification
Languages
Education
DTU
M.Sc., Synthetic Aperture Radiometer · Synthetic Aperture Radiometer · Lyngby, Denmark
Profile
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