Anoop P.
Sr.Staff Engineer - AMS Verification
Experience
Mar 2018 - Dec 2023
5 years 10 monthsLinz, Austria
Sr.Staff Engineer - AMS Verification
Infineon Technologies
- Verification of 77 GHz automobile radar chip
- Verifying top level analog/mixed signal design, doing co-simulations of mixed signal blocks and full chip using Cadence Spectre, Virtuoso and Xcelium tools
- Writing behavioral real number models in System Verilog
- Innovating AMS verification methodology
- Schematic vs model verification
- FUSA verification for radar systems with different ASIL requirements
- Involved in fault injection and simulation process
- Simulating various fault scenarios to assess the impact on radar performance and safety
- Performance verification: verifying that the radar meets performance requirements under various conditions and with fault tolerance enabled
- Writing real number models to inject faults (for example injecting faults in signal chain and power management blocks)
- Knowhow of V shaped model ISO 26262
Nov 2016 - Feb 2018
1 year 4 monthsBengaluru, India
Sr.Staff Engineer - AMS Verification
Mindlance TechSolutions Pvt Ltd
- Leading a team and individual contributor working as a consultant in Analog Devices, Bangalore to verify full chip and block level mixed signal IC of an automobile magnetic sensor chip
- Verifying power management circuit at top level and block level
- Verifying signal chain of IC
- Verifying top level mixed signal design, doing co-simulations of mixed signal blocks and full chip
- Creating top level test-benches by using AMS and digital simulation tools to verify the IC
- Writing System Verilog Assertions and using UVM-AMS methodology
- Using Eplanner to create verification plan
- Using Analog Devices in house simulator with Cadence ADE
Feb 2013 - Jun 2015
2 years 5 monthsGeorge Town, Malaysia
Member Technical Staff
Altera Corporation Sdn Bhd
- Leading a small team for AMS methodology and verification of FPGA
Jun 2011 - Aug 2012
1 year 3 monthsGeorge Town, Malaysia
Senior Circuit DA Engineer
Intel Malaysia
- Worked on circuit optimization using Cadence ADE with respect to area and speed
Feb 2006 - May 2011
5 years 4 monthsNoida, India
Senior Member Technical Staff
Mentor Graphics India Pvt Ltd
- Worked as corporate application engineer supporting various customers in Asia and Europe, implementing analog and analog mixed signal flow for design entry and simulation as well as RTL design using Eldo and Eldo-RF, Questa-ADMS, ADiT and IC Flow
- Gave presentations in India for multiple customers
- Trained in India and Singapore for ELDO, ADiT and AMS tools
Jun 2004 - Dec 2005
1 year 7 monthsBengaluru, India
Hardware Engineer
Silicon Gateway Pvt Ltd
- Worked on Tanner tools: S-Edit, T-Spice and L-Edit; Xilinx; and digital simulator Modelsim from Mentor Graphics
- Delivered training to customers on Tanner tool and Modelsim tool
- Gave technical presentations at customer’s site to promote hi-tech product lines as part of concept selling initiatives
Summary
Strong understanding of design methodologies having worked in busy Analog Mixed signal and digital environments. Seeking a role in Verification with scope for technical challenge and career progression.
- Almost 18 plus years of experience in Analog Mixed Signal Verification.
- Creating verification environment and writing testbenches in Verilog/System Verilog with SVA
- Knowledge and experience with FUSA verification ISO 260262
- Involved in Verifying RF/Analog Mixed Signal IC at Top Level and Block level
- Involved in Analog /Mixed Signal Behavioral Model Development using SystemVerilog/Verilog-AMS/Verilog-A
- Modeling Real Number Models using System Verilog (SV RNM)
- Scripting and Automation using language: Perl and Tcl
- Verification Methodology: Using UVM, System Verilog
- Tools used: AMS simulations: Cadence ADE,ADE-XL, Questa-ADMS, ADICE
- Analog simulations using ELDO, Spectre, APS, ELDO-RF, ADIT, ADICE
- Digital simulations using: Xcelium, Modelsim/Questasim
Languages
Marathi
NativeEnglish
AdvancedHindi
AdvancedKannada
AdvancedGerman
ElementaryEducation
Oct 1997 - Jun 2001
Karnataka University Dharwad
Bachelor of Engineering · Electronics and Communication Engineering · Dharwad, India
Oct 1994 - Jun 1997
Board of Technical Education
Diploma in Electronics & Communication Engineering · Electronics & Communication Engineering · Bengaluru, India
Oct 1993 - Jun 1994
Board of Maharashtra
SSC (10th) · SSC (10th) · Pune, India
Certifications & licenses
CMOS RF IC Design Course
Indian Institute of technology (IIT) Delhi
PG Diploma VLSI design course
Sandeepani School of VLSI Design
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