Jonathan L. - 3-Stage Ring Oscillator

Santa Clara, United States

Experience

Using Cadence Virtuoso, designed a 3-stage ring oscillator circuit containing minimal PVT variation.
Enlarged transistor width of a regular CMOS inverter (400 nm to 200 µm for PMOS; 400 nm to 100 µm for NMOS) and length from 280 nm to 2 µm and added two more inverters for quicker switching frequency.
Simulated at ± 10 % variation of VDD=1.08 V, 1.32 V, each containing process corners of ss and ff in -40 °C and 125 °C.

Performed HSPICE simulation and created 90 nm layout of 4-bit CLA adder using Manchester carry chain as bottom level.

Conducted various feature sets in data analytic model pipeline to achieve the highest detection accuracy possible based on the dataset composed of artificial and anomalous HVAC sounds.

Developed efficient data structures for a maze application, including a deque (circular doubly-linked list) and a scalable hash set with chaining, optimizing memory usage and collision handling.
Implemented a dynamic waiting list system using linked lists to manage people in line at restaurants, ensuring efficient insertion, deletion, and traversal of queue elements based on the specified priority.

Familiarized with AFM, SEM, CZ furnace, ellipsometer, and ultraviolet high vacuum deposition system in Center for Nanostructures.
Noted that AFM’s probe tips need newer ones for precise imaging and the vacuum pump in deposition system needed 10–15 minutes of calibration prior to measuring pressure and ion gauge of thin aluminum deposition on silicon dioxide.
Performed an inspection/performance check on the ellipsometer based on past manuals/datasheet and discovered that thin oxide deposited on Si(100) wafer has 1.5× change in polarization and 1.5× film thickness than thin nitride.
Reviewed and familiarized with the lab operational manuals of SEM, CZ furnace, and ultraviolet high deposition equipment based on operational procedures and safety protocols, supervised by CNS lab technician.

Demonstrated characterization of a forward-biased PN junction diode with various virtual elements/alloys by measuring its respective power efficiency via an I-V curve using Sentaurus Visual.

Documented a technical user manual that introduced device characterization by using a 4200-SCS/F Parameter Analyzer and its ATE platforms to characterize the discrete devices (BJT, enhancement-mode MOSFETs, diodes, MOS Cap) performance optimization while referencing transistor-level datasheet specifications.
Applied ATE characterization methods to align lab measurements with testbench requirements, contributing to product reliability, and sustaining cost-reduction initiatives.

Ranked the most energy-efficient amongst the five most sold video game consoles, by calculating the power consumed during active and idle/standby.
Measured the energy efficiency, memory storage, power mode consumption, and motherboard consumption in order to allow users to distinguish which console fits their gameplay experience.